DATA SHEET MOS INTEGRATED CIRCUIT PD78F9436, 78F9456 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The PD78F9436 and 78F9456 belong to the PD789436, 789456 Subseries (for LCD drivers) in the 78K/0S Series. The PD78F9436 has flash memory in place of the internal ROM of the PD789435 and 789436, and the PD78F9456 has flash memory in place of the internal ROM of the PD789455 and 789456. Because flash memory allows the program to be written and erased electrically with the device mounted on the board, this product is ideal for the evaluation stages of system development, small-scale production, and rapid development of new products. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD789426, 789436, 789446, 789456 Subseries User's Manual: U15075E 78K/0S Series User's Manual Instructions: U11047E FEATURES * Pin compatible with mask ROM version (except VPP pin) * Flash memory and RAM capacities Item Flash Memory Part Number PD78F9436 Data Memory Internal High-Speed RAM 16 KB 512 bytes PD78F9456 LCD Display RAM 5 x 4 bits 15 x 4 bits * Minimum instruction execution time can be changed from high-speed (0.4 s at 5.0 MHz operation with main system clock) to ultra-low-speed (122 s at 32.768 kHz operation with subsystem clock). * I/O ports : 40 (PD78F9436) : 30 (PD78F9456) * Timer: 5 channels * A/D converter 10-bit resolution: 6 channels * Serial interface: 1 channel * LCD controller/driver Segment signals: 5, common signals: 4 (PD78F9436) Segment signals: 15, common signals: 4 (PD78F9456) * Power supply voltage: VDD = 1.8 to 5.5 V APPLICATIONS Portable audio systems, cameras, healthcare equipment, etc. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U15379EJ1V0DS00 (1st edition) Date Published June 2001 N CP(K) Printed in Japan (c) 2001 1999 1996, PD78F9436, 78F9456 ORDERING INFORMATION Part Number Package PD78F9436GK-9ET 64-pin plastic TQFP (12 x 12) PD78F9456GK-9ET 64-pin plastic TQFP (12 x 12) 2 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 78K/0S SERIES LINEUP The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 30-pin 28-pin PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789074 with enhanced timer and increased ROM and RAM capacity PD789026 with enhanced timer On-chip UART and capable of low voltage (1.8 V) operation PD789046 PD789026 PD789088 PD789074 PD789014 Small-scale package, general-purpose applications and A/D converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789177Y PD789167Y PD789167 with enhanced A/D converter PD789104A with enhanced timer PD789146 with enhanced A/D converter PD789104A with added EEPROMTM PD789124A with enhanced A/D converter RC oscillation version of the PD789104A PD789104A with enhanced A/D converter PD789026 with added A/D converter and multiplier Inverter control 44-pin PD789842 On-chip inverter controller and UART VFD drive 78K/0S Series 52-pin PD789871 Total display outputs: 25 LCD drive 64-pin 64-pin 52-pin PD789488 PD789477 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 52-pin PD789327 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 x 4) SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789407A with enhanced A/D converter SIO, 8-bit A/D converter, and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D converter SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 SIO and on-chip voltage booster type LCD (24 x 4) 8-bit A/D converter and on-chip voltage booster type LCD SIO and resistance division type LCD Dot LCD drive 144-pin 88-pin PD789835 PD789830 Segment/common outputs: 96 Segments: 40, commons: 16 ASSP 64-pin 44-pin 44-pin 20-pin 20-pin Remark PD789803 PD789800 PD789840 PD789861 PD789860 For PC keyboard, on-chip USB HUB function For PC keyboard, on-chip USB function For keypad, on-chip POC RC oscillation version of the PD789860 For keyless entry, on-chip POC and key return circuit TM VFD (Vacuum Fluorescent Display) is referred to as "FIP " (fluorescent Indicator panel) in some documents, but the functions of the two are the same. Data Sheet U15379EJ1V0DS 3 PD78F9436, 78F9456 The major functional differences among the subseries are listed below. Function Subseries Name Small-scale package, generalpurpose applications Small-scale package, generalpurpose applications and A/D converter ROM Capacity Timer 8-Bit 16-Bit Watch WDT Serial Interface I/O 16 K PD789026 4 K to 16 K PD789088 16 K to 32 K 3 ch PD789074 2 K to 8 K 1 ch PD789014 2 K to 4 K 2 ch - PD789177 16 K to 24 K 3 ch 1 ch 1 ch 1 ch 1 ch 1 ch - - 1 ch (UART: 1 ch) Remarks 34 1.8 V - 1.8 V - 24 22 1 ch 1 ch PD789167 - 8 ch 8 K to 16 K - VDD MIN. Value (Bytes) PD789046 PD789156 8-Bit 10-Bit A/D A/D - 1 ch PD789146 PD789134A 2 K to 8 K 8 ch 1 ch (UART: 1 ch) - 31 20 - 4 ch 4 ch - - 4 ch 4 ch - PD789114A - 4 ch PD789104A 4 ch - PD789124A On-chip EEPROM RCoscillation version - Inverter control PD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch - 1 ch (UART: 1 ch) 30 4.0 V - VFD drive PD789871 4 K to 8 K 3 ch - 1 ch 1 ch - - 1 ch 33 2.7 V - LCD drive PD789488 32 K 3 ch 1 ch 1 ch 1 ch 1.8 V - 24 K 8 ch 2 ch (UART: 1 ch) - 45 PD789477 7 ch 1 ch (UART: 1 ch) - 43 30 PD789417A 12 K to PD789407A 24 K PD789456 PD789446 12 K to 16 K - 7 ch 2 ch PD789436 PD789426 PD789316 - 8 ch 8 K to 16 K - 6 ch 6 ch - - 6 ch 6 ch - - 40 2 ch (UART: 1 ch) 23 RCoscillation version PD789306 PD789427 - 4 K to 24 K - 1 ch PD789327 Dot LCD drive ASSP - PD789835 24 K to 60 K 6 ch - PD789830 24 K 1 ch 1 ch PD789803 8 K to 16 K 2 ch - PD789800 8K PD789840 PD789861 1 ch 1 ch - 1 ch 3 ch - 4 ch 4K - 18 1 ch 21 - 1 ch (UART: 1 ch) 28 30 2.7 V - 2 ch 41 3.6 V (USB: 1 ch) 31 4.0 V 1 ch 29 2.8 V 14 1.8 V RCoscillation version, on-chip EEPROM - PD789860 - 1.8 V - - On-chip EEPROM Note 10-bit timer: 1 channel 4 - Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 OVERVIEW OF FUNCTIONS PD78F9436 Item Internal memory Flash memory 16 KB High-speed RAM 512 bytes LCD display RAM 5 x 4 bits PD78F9456 15 x 4 bits Minimum instruction execution time 0.4 s/1.6 s (@ 5.0 MHz operation with main system clock) 122 s (@ 32.768 kHz operation with subsystem clock) General-purpose registers 8 bits x 8 registers Instruction set * 16-bit operation * Bit manipulation (set, reset, test) I/O ports Total: * CMOS I/O: * CMOS input: * N-ch open drain: Timers * * * * A/D converter 10-bit resolution x 6 channels Serial interface * Switchable between 3-wire serial I/O mode and UART mode: 1 channel LCD controller/driver * Segment signal outputs: 5 (max.) * Common signal outputs: 4 (max.) Vectored interrupt Maskable sources Non-maskable Internal: 9, external: 5 Internal: 1 Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = -40 to +85C Package 64-pin plastic TQFP (12 x 12) 16-bit timer: 8-bit timer: Watch timer: Watchdog timer: 40 30 6 4 Total: * CMOS I/O: * CMOS input: * N-ch open drain: 30 20 6 4 1 channel 2 channels 1 channel 1 channel Data Sheet U15379EJ1V0DS * Segment signal outputs: 15 (max.) * Common signal outputs: 4 (max.) 5 PD78F9436, 78F9456 CONTENTS 1. PIN CONFIGURATION (Top View) ...................................................................................................................... 7 1.1 Pin Configuration of the PD78F9436 (Top View) ................................................................................. 7 1.2 Pin Configuration of the PD78F9456 (Top View) ................................................................................. 8 2. BLOCK DIAGRAM .............................................................................................................................................. 10 3. PIN FUNCTIONS................................................................................................................................................. 11 3.1 Port Pins.................................................................................................................................................. 11 3.2 Non-Port Pins ......................................................................................................................................... 12 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...................................................... 13 4. MEMORY SPACE ............................................................................................................................................... 15 5. FLASH MEMORY PROGRAMMING................................................................................................................... 16 6. 5.1 Selecting Communication Mode ........................................................................................................... 16 5.2 Function of Flash Memory Programming............................................................................................. 17 5.3 Connecting Flashpro III.......................................................................................................................... 17 5.4 Example of Settings for Flashpro III (PG-FP3) ..................................................................................... 19 OVERVIEW OF INSTRUCTION SET .................................................................................................................. 20 6.1 Conventions............................................................................................................................................ 20 6.2 List of Operations................................................................................................................................... 22 7. ELECTRICAL SPECIFICATIONS ....................................................................................................................... 27 8. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFRENCE VALUES).............................. 42 9. PACKAGE DRAWINGS ...................................................................................................................................... 44 10. RECOMMENDED SOLDERING CONDITIONS .................................................................................................. 45 APPENDIX A. DIFFERENCES BETWEEN PD78F9436, 78F9456 AND MASK ROM VERSIONS ................ 46 APPENDIX B. DEVELOPMENT TOOLS................................................................................................................... 47 APPENDIX C. RELATED DOCUMENTS .................................................................................................................. 49 6 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 1. PIN CONFIGURATION (TOP VIEW) 1.1 Pin Configuration of the PD78F9436 (Top View) 64-pin plastic TQFP (12 x 12) P20 P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 P30/INTP0/CPT90 P31/INTP1/TO50/TMI60 P32/INTP2/TO60 P33/INTP3/TO61 P10 P11 AVSS P60/ANI0 P61/ANI1 PD78F9436GK-9ET 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 AVDD P72 P71 P70 P81 P80 P97 P96 P95 P94 P93 P92 CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 P90 P91 P50 P51 P52 P53 VPP XT1 XT2 VDD VSS X1 X2 RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3 Cautions 1. Connect the VPP pin directly to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. Data Sheet U15379EJ1V0DS 7 PD78F9436, 78F9456 1.2 Pin Configuration of the PD78F9456 (Top View) 64-pin plastic TQFP (12 x 12) P20 P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 P30/INTP0/CPT90 P31/INTP1/TO50/TMI60 P32/INTP2/TO60 P33/INTP3/TO61 P10 P11 AVSS P60/ANI0 P61/ANI1 PD78F9456-9ET 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 P50 P51 P52 P53 VPP XT1 XT2 VDD VSS X1 X2 RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3 Cautions 1. Connect the VPP pin directly to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 8 Data Sheet U15379EJ1V0DS P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 AVDD P72 P71 P70 S14 S13 S12 S11 S10 S9 S8 S7 PD78F9436, 78F9456 Note ANI0 to ANI5: Analog input P90 to P97 ASCK20: Asynchronous serial input RESET: : Port 9 Reset AVDD: Analog power supply RxD20: Receive data AVSS: Analog ground SS20: Serial chip select BZO90: Buzzer output S0 to S14: Segment output CAPH, CAPL: LCD power supply capacitance control SCK20: Serial clock COM0 to COM3: Common output SI20: Serial input CPT90: Capture trigger input SO20: Serial output INTP0 to INTP3: External interrupt input TMI60: Timer input KR0 to KR3: Key return TO90, TO50, TO60, P00 to P03: Port 0 TO61: Timer output P10, P11: Port 1 TxD20: Transmit data P20 to P26: Port 2 VDD: Power supply P30 to P33: Port 3 VLC0 to VLC2: LCD power supply P50 to P53: Port 5 VPP: Programming power supply P60 to P63: Port 6 VSS: Ground P70 to P72: P80 to P81 Note : Port 7 X1, X2: Crystal (Main system clock) Port 8 XT1, XT2: Crystal (Subsystem clock) Note PD78F9436 only Data Sheet U15379EJ1V0DS 9 PD78F9436, 78F9456 2. BLOCK DIAGRAM TO50/TMI60/P31 TO60/P32 TO61/P33 TMI60/TO50/P31 TO90/P26 CPT90/P30 BZO90/P21 8-bit timer 50 Cascaded 16-bit timer/ 8-bit event timer/event counter counter 60 Watchdog timer SCK20/ASCK20/P23 SO20/TxD20/P24 SI20/RxD20/P25 SS20/P22 P00 to P03 Port 1 P10, P11 Port 2 P20 to P26 Port 3 P30 to P33 Port 5 P50 to P53 Port 6 P60 to P65 Port 7 P70 to P72 16-bit timer 90 Watch timer ANI0/P60 to ANI5/P65 AVDD AVSS Port 0 Flash memory 78K/0S CPU core A/D converter RAM space for LCD data RAM Serial interface 20 Port 8Note P80, P81Note Port 9Note P90 to P97Note System control S0 to S4 (S0 to S14) COM0 to COM3 VLC0 to VLC2 CAPH CAPL INTP0/P30 LCD controller driver INTP1/P31 Interrupt control VDD VSS VPP Note PD78F9436 only Remark 10 RESET X1 X2 XT1 XT2 Descriptions in parentheses are for the PD78F9456. Data Sheet U15379EJ1V0DS INTP2/P32 INTP3/P33 KR0/P00 to KR3/P03 PD78F9436, 78F9456 3. PIN FUNCTIONS 3.1 Port Pins Pin Name I/O Function After Reset Alternate Function P00 to P03 I/O Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by a software setting. Input KR0 to KR3 P10, P11 I/O Port 1. 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by a software setting. Input -- P20 I/O Port 2. 7-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by a software setting. Input -- P21 P22 P23 BZO90 SS20 SCK20/ASCK20 P24 SO20/TxD20 P25 SI20/RxD20 P26 TO90 P30 I/O P31 P32 P33 Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by a software setting. Input INTP0/CPT90 INTP1/TO50/TMI60 INTP2/TO60 INTP3/TO61 P50 to P53 I/O Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. Input -- P60 to P65 Input Port 6. 6-bit input port. Input P70 to P72 I/O Port 7. 3-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by a software setting. Input -- P80, P81Note I/O Port 8. 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by a software setting. Input -- P90 to P97Note I/O Port 9. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by a software setting. Input -- ANI0 to ANI5 Note PD78F9436 only Data Sheet U15379EJ1V0DS 11 PD78F9436, 78F9456 3.2 Non-Port Pins Pin Name INTP0 I/O Input INTP1 Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Alternate Function P30/CPT90 Input P31/TO50/TMI60 INTP2 P32/TO60 INTP3 P33/TO61 KR0 to KR3 Input Key return signal detection Input P00 to P03 SS20 Input Serial interface (SIO20) chip select Input P22 SCK20 I/O Serial interface (SIO20) serial clock input/output Input P23/ASCK20 SI20 Input SIO20 serial interface serial data input Input P25/RxD20 SO20 Output SIO20 serial interface serial data output Input P24/TxD20 ASCK20 I/O Asynchronous serial interface serial clock input Input P23/SCK20 RxD20 Input Asynchronous serial interface serial data input Input P25/SI20 TxD20 Output Asynchronous serial interface serial data output Input P24/SO20 TO90 Output 16-bit timer (TM90) output Input P26 CPT90 Input Capture edge input Input P30/INTP0 TO50 Output 8-bit timer (TM50) output Input P31/INTP1/TMI60 TO60 Output 8-bit timer (TM60) output Input P32/INTP2 TO61 Output 8-bit timer (TM60) output Input P33/INTP3 TMI60 Input External count clock input to 8-bit timer (TM60) Input P31/INTP1/TO50 ANI0 to ANI5 Input A/D converter analog inputs Input P60 to P65 S0 to S4 Output Segment signal outputs for LCD controller/driver Output -- Output Segment signal outputs for LCD controller/driver Output -- COM0 to COM3 Output Common signal outputs for LCD controller/driver Output -- VLC0 to VLC2 -- LCD drive voltage -- -- CAPH -- Connection pin for LCD driver's capacitor -- -- CAPL -- -- -- -- -- -- -- -- -- -- -- Note S5 to S14 X1 X2 XT1 XT2 RESET Input Connecting crystal resonator for main system clock oscillation -- Input Connecting crystal resonator for subsystem clock oscillation -- Input System reset input Input -- VDD -- Positive power supply for ports -- -- VSS -- Ground potential -- -- AVDD -- A/D converter analog potential -- -- AVSS -- A/D converter ground potential -- -- VPP -- Flash memory programming mode setting. High-voltage application for program write/verify. In normal operation mode, connect directly to VSS. -- -- Note PD78F9456 only 12 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins Pin Name I/O Circuit Type P00 to P03 8-A P10, P11 5-A P20 8-A I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 Input: Independently connect to VSS via a resistor. Output: Leave open. P30/INTP0/CPT90 P31/INTP1/TO50/ TMI60 P32/INTP2/TO60 P33/INTP3/TO61 P50 to P53 13-V Input: Independently connect to VDD via a resistor. Output: Leave open. P60/ANI0 to P65/ANI5 9-C Input Connect directly to VDD or VSS. P70 to P72 5-A I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. 17 Output Leave open. COM0 to COM3 18 -- VLC0 to VLC2 -- Note 1 P80, P81 P90 and P97Note 1 S0 to S4 Note 2 S5 to S14 CAPH, CAPL XT1 Input Connect to VSS. -- XT2 Leave open. AVSS Connect to VSS. AVDD Connect to VDD. RESET 2 VPP -- Input -- -- Connect directly to VSS. Notes 1. PD78F9436 only 2. PD78F9456 only Data Sheet U15379EJ1V0DS 13 PD78F9436, 78F9456 Figure 3-1. Pin Input/Output Circuits Type 2 Type 9-C IN Comparator P-ch N-ch IN + AVSS VREF (Threshold voltage) Schmitt-triggered input with hysteresis characteristics Type 5-A Input enable Type 13-V VDD Pull-up enable P-ch IN/OUT Output data Output disable VDD Data N-ch P-ch VSS IN/OUT Output disable Input enable N-ch Middle-voltage input buffer VSS Input enable Type 8-A Type 17 VDD VLC0 P-ch Pull-up enable P-ch VLC1 P-ch N-ch P-ch VDD Data SEG data P-ch OUT N-ch IN/OUT Output disable VLC2 N-ch VLC1 P-ch P-ch N-ch P-ch N-ch OUT COM data N-ch P-ch P-ch VLC2 N-ch N-ch 14 N-ch N-ch VSS Type 18 VLC0 P-ch Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 4. MEMORY SPACE Figure 4-1 shows the memory map. Figure 4-1. Memory Map FFFFH Special function registers (SFRs) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH Reserved mmmm + 1H mmmmH Data memory space LCD display RAMNote FA00H F9FFH 4000H 3FFFH 3FFFH Reserved Program area Program memory space 0080H 007FH Flash memory 16384 x 8 bits CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H Note Vector table area The capacity of the LCD display RAM varies depending on the product (see following table). Part Number Last Address of LCD display RAM mmmmH PD78F9436 FA04H PD78F9456 FA0EH Data Sheet U15379EJ1V0DS 15 PD78F9436, 78F9456 5. FLASH MEMORY PROGRAMMING The program memory that is incorporated in the PD78F9436 and 78F9456 is flash memory. With flash memory, it is possible to write programs on-board. Writing is performed by connecting a dedicated flash programmer (Flashpro III (Part No. FL-PR3, PG-FP3)) to the host machine and the target system. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd. 5.1 Selecting Communication Mode Writing to flash memory is performed using the Flashpro III in a serial communication mode. Select one of the communication modes in Table 5-1. The selection of the communication mode is made by using the format shown in Figure 5-1. Each communication mode is selected using the number of VPP pulses shown in Table 5-1. Table 5-1. List of Communication Mode PinsNote Communication Mode 3-wire serial I/O UART VPP Pulses SCK20/P23 SO20/P24 SI20/P25 0 P00/KR0 (serial clock input) P01/KR1 (serial data output) P02/KR2 (serial data input) 1 TxD20/P24 RxD20/P25 8 Note Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as immediately after reset. If the external device connected to the port does not acknowledge the port state immediately after reset, handling such as connecting to VDD or VSS via a resistor or connecting to is required. Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 5-1. Figure 5-1. Format of Communication Mode Selection 10 V VPP VDD 1 VSS RESET VDD VSS 16 Data Sheet U15379EJ1V0DS 2 n PD78F9436, 78F9456 5.2 Function of Flash Memory Programming Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 5-2 shows the major functions of flash memory programming. Table 5-2. Major Function of Flash Memory Programming Function Description Batch erase Deletes the entire memory contents. Batch blank check Checks the deletion status of the entire memory. Data write Performs a write operation to the flash memory based on the write start address and the number of data to be written (number of bytes). Batch verify Compares the entire memory contents with the input data. 5.3 Connecting Flashpro III The connection of the Flashpro III and the PD78F9436 and 78F9456 differs according to the communication mode (3-wire serial I/O or UART). The connections for each communication mode are shown in Figures 5-2 and 5-3, respectively. Figure 5-2. Connection Example of Flashpro III When Using 3-Wire Serial I/O Mode (1/2) PD78F9436, 78F9456 Flashpro III VPPnNote VPP VDD VDD RESET RESET CLK X1 SCK SCK20 SO SI20 SI SO20 VSS GND Note n = 1, 2 Data Sheet U15379EJ1V0DS 17 PD78F9436, 78F9456 Figure 5-2. Connection Example of Flashpro III When Using 3-Wire Serial I/O Mode (2/2) PD78F9436, 78F9456 Flashpro III VPPnNote VPP VDD VDD RESET CLK X1 SCK P00/KR0 (Serial clock) SO P02/KR2 (Serial input) SI P01/KR1 (Serial output) GND Note RESET VSS n = 1, 2 Figure 5-3. Connection Example of Flashpro III When Using UART Mode PD78F9436, 78F9456 Flashpro III VPPnNote VPP VDD VDD RESET CLK 18 X1 SO RxD20 SI TxD20 GND Note RESET n = 1, 2 Data Sheet U15379EJ1V0DS VSS PD78F9436, 78F9456 5.4 Example of Settings for Flashpro III (PG-FP3) When writing to flash memory using Flashpro III (PG-FP3), make the following settings. <1> Load a parameter file. <2> Select the mode of serial communication and serial clock with a type command. <3> Make the settings according to the example of settings for PG-FP3 shown below. Table 5-3. Example of Settings for PG-FP3 Communication Mode 3-wire serial I/O VPP Pulse NumberNote 1 Example of Settings for PG-FP3 COMM PORT SIO-ch0 CPU CLK On Target Board 0 In Flashpro On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT SIO-ch1 CPU CLK On Target Board 1 In Flashpro UART On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT UART-ch0 CPU CLK On Target Board On Target Board 4.1943 MHz UART BPS 9600 bpsNote 2 8 Notes 1. This is the number of VPP pulses that are supplied by the Flashpro III at serial communication initialization. The pins that will be used for communication are determined according to this number. 2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. Remark COMM PORT: Serial port selection SIO CLK: Serial clock frequency selection CPU CLK: Input CPU clock source selection Data Sheet U15379EJ1V0DS 19 PD78F9436, 78F9456 6. OVERVIEW OF INSTRUCTION SET This section lists the instruction set for the PD78F9436 and 78F9456. 6.1 Conventions 6.1.1 Operand expressions and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand expression (see the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and symbols, #, !, $, and [ ] are key words and are described as they are. The meaning of each symbol is described below. * #: Immediate data specification * $: * !: Absolute address specification * [ ]: Indirect address specification Relative address specification For immediate data, enter an appropriate numeric value or a label. When using a label, be sure to enter the #, !, $ and [ ] symbols. For operand register expressions, r and rp, either function names (X, A, C, etc.) or absolute names (names in parenthesis in the table below, R0, R1, R2, etc.) can be used for the description. Table 6-1. Operand Expressions and Description Methods Expression Description Method r rp sfr X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr saddrp FE20H to FF1FH: immediate data or label FE20H to FF1FH: immediate data or label (even addresses only) addr16 addr5 0000H to FFFFH: immediate data or label (even addresses only for 16-bit data transfer instruction) 0040H to 007FH: immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label 20 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 6.1.2 Description of "Operation" column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag indicating non-maskable interrupt servicing in progress ( ): Memory contents indicated by address or register contents in parenthesis XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : : Exclusive logical sum (exclusive OR) Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 6.1.3 Description of "Flag" column (Blank): Unchanged 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is restored Data Sheet U15379EJ1V0DS 21 PD78F9436, 78F9456 6.2 List of Operations Mnemonic Operand Bytes Clocks Operation Flag Z MOV XCH r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte A, r Note 1 2 4 Ar r, A Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL + byte] 2 6 A (HL + byte) [HL + byte], A 2 6 (HL + byte) A 1 4 AX 2 6 Ar A, saddr 2 6 A (saddr) A, sfr 2 6 A (sfr) A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL + byte] 2 8 A (HL + byte) rp, #word 3 6 rp word A, X A, r MOVW XCHW Note 2 AX, saddrp 2 6 AX (saddrp) saddrp, AX 2 8 (saddrp) AX AX, rp Note 3 1 4 AX rp rp, AX Note 3 1 4 rp AX AX, rp Note 3 1 8 AX rp AC CY x x x x x x Notes 1. Except r = A 2. Except r = A, X 3. Only when rp = BC, DE, HL Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). 22 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 Mnemonic Operand Bytes Clocks Operation Flag Z ADD ADDC SUB SUBC AND Remark AC CY A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A, CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL + byte] 2 6 A, CY A + (HL + byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) x x x A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL + byte] 2 6 A, CY A - (HL + byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). Data Sheet U15379EJ1V0DS 23 PD78F9436, 78F9456 Mnemonic Operand Bytes Clocks Operation Flag Z AC CY A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL + byte] 2 6 A A (HL + byte) x A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL + byte] 2 6 A - (HL + byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am - 1 Am) x 1 time x ROL A, 1 1 2 (CY, A0 A7, Am + 1 Am) x 1 time x RORC A, 1 1 2 (CY A0, A7 CY, Am - 1 Am) x 1 time x ROLC A, 1 1 2 (CY A7, A0 CY, Am + 1 Am) x 1 time x OR XOR CMP DEC Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). 24 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 Mnemonic Operand Bytes Clocks Operation Flag Z AC CY saddr. bit 3 6 (saddr. bit) 1 sfr. bit 3 6 sfr. bit 1 A. bit 2 4 A. bit 1 PSW. bit 3 6 PSW. bit 1 [HL]. bit 2 10 (HL). bit 1 saddr. bit 3 6 (saddr. bit) 0 sfr. bit 3 6 sfr. bit 0 A. bit 2 4 A. bit 0 PSW. bit 3 6 PSW. bit 0 [HL]. bit 2 10 (HL). bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 PCH (SP + 1), PCL (SP), SP SP + 2 RETI 1 8 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X SET1 CLR1 PUSH POP MOVW BR Remark x x x x x x R R R R R R One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). Data Sheet U15379EJ1V0DS 25 PD78F9436, 78F9456 Mnemonic Operand Bytes Clocks Operation Flag Z BC $addr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr. bit = 1 A. bit, $addr16 3 8 PC PC + 3 + jdisp8 if A. bit = 1 PSW. bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW. bit = 1 saddr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr. bit = 0 A. bit, $addr16 3 8 PC PC + 3 + jdisp8 if A. bit = 0 PSW. bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW. bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1 (Enable Interrupt) DI 3 6 IE 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode BF DBNZ Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC). 26 AC CY Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Power supply voltage Symbol VDD Conditions VDD = AVDD Ratings Unit -0.3 to +6.5 V AVDD -0.3 to +10.5 VPP Input voltage VI1 P00 to P03, P10, P11, P20 to P26, P30 to P33, P60 to P65, P70 to P72, P80Note 1, P81Note 1, P90 to P97Note 1, X1, X2, XT1, XT2, RESET VI2 P50 to P53 Output voltage VO Output current, high IOH Output current, low Operating ambient temperature IOL TA N-ch open drain -0.3 to VDD + 0.3 -0.3 to +13 V V Note 2 -0.3 to VDD + 0.3 V Per pin -10 mA Total for all pins -30 mA Per pin 30 mA Total for all pins 160 mA -40 to +85 C 10 to 40 C -40 to +125 C In normal operation mode During flash memory programming Storage temperature V Note 2 Tstg Notes 1. For PD78F9436 2. 6.5 V or less Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U15379EJ1V0DS 27 PD78F9436, 78F9456 Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit VPP X1 Ceramic resonator C1 VPP X1 Crystal resonator C1 External clock X1 X1 X2 Parameter Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 C2 X2 X2 X2 OPEN MIN. 1.0 After VDD reaches oscillation voltage range MIN. Oscillation frequency(fX)Note 1 Oscillation stabilization timeNote 2 C2 Conditions 1.0 VDD = 4.5 to 5.5 V TYP. MAX. Unit 5.0 MHz 4 ms 5.0 MHz 10 ms 30 ms X1 input frequency (fX)Note 1 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) 85 500 ns X1 input frequency (fX)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz X1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 28 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit VPP XT1 Crystal resonator C3 External clock XT1 XT2 R C4 XT2 Parameter Conditions Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s VDD = 4.5 to 5.5 V XT1 input frequency (fXT)Note 1 XT1 input high-/low-level width (tXTH, tXTL) 10 32 35 kHz 14.3 15.6 s Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U15379EJ1V0DS 29 PD78F9436, 78F9456 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Output current, low Output current, high Input voltage, high Symbol IOL IOH VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high Output voltage, low VOH VOL1 VOL2 Conditions MAX. Unit Per pin 10 mA All pins 80 mA Per pin -1 mA All pins -15 mA 0.7VDD VDD V 0.9VDD VDD V 0.7VDD 12 V 0.9VDD 12 V 0.8VDD VDD V 0.9VDD VDD V VDD - 0.5 VDD V VDD - 0.1 VDD V 0 0.3VDD V 0 0.1VDD V 0 0.3VDD V 0 0.1VDD V 0 0.2VDD V 0 0.1VDD V 0 0.4 V 0 0.1 V P10, P11, P60 to P65, P70 to P72, P80Note, P81Note, P90 to P97Note VDD = 2.7 to 5.5 V P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V RESET, P00 to P03, P20 to P26, P30 to P33 VDD = 2.7 to 5.5 V X1, X2, XT1, XT2 VDD = 4.5 to 5.5 V P10, P11, P60 to P65, P70 to P72, P80Note, P81Note, P90 to P97Note VDD = 2.7 to 5.5 V P50 to P53 VDD = 2.7 to 5.5 V RESET, P00 to P03, P20 to P26, P30 to P33 VDD = 2.7 to 5.5 V X1, X2, XT1, XT2 VDD = 4.5 to 5.5 V MIN. TYP. VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V VDD = 1.8 to 5.5 V, IOH = -100 A VDD - 0.5 V P00 to P03, P10, P11, P20 to P26, P30 to P33, P60 to P65, P70 to P72, P80Note, P81Note, P90 to P97Note, X1, X2, XT1, XT2 P50 to P53 4.5 VDD 5.5 V, IOL = 10 mA 1.0 V 1.8 VDD < 4.5 V, IOL = 400 A 0.5 V 4.5 VDD < 5.5 V, IOL = 10 mA 1.0 V 1.8 VDD < 4.5 V, IOL = 1.6 mA 0.4 V Note PD78F9436 only Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 30 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Input leakage current, high Symbol ILIH1 Conditions VI = VDD ILIH2 Input leakage current, low MIN. TYP. MAX. Unit P00 to P03, P10, P11, P20 to P26, P30 to P33, P60 to P65, P70 to P72, P80Note 1, P81Note 1, P90 to P97Note 1, RESET 3 A X1, X2, XT1, XT2 20 A ILIH3 VI = 12 V P50 to P53 (N-ch open drain) 20 A ILIL1 VI = 0 V P00 to P03, P10, P11, P20 to P26, P30 to P33, P60 to P65, P70 to P72, P80Note 1, P81Note 1, P90 to P97Note 1, RESET -3 A X1, X2, XT1, XT2 -20 A ILIL2 ILIL3 Note 2 -3 P50 to P53 (N-ch open drain) A Output leakage current, ILOH high VO = VDD 3 A Output leakage current, ILOL low VO = 0 V -3 A Software pull-up resistor VI = 0 V 200 k R1 P00 to P03, P10, P11, P20 to P26, P30 to P33, P70 to P72, P80Note 1, P81Note 1, P90 to P97Note 1 50 100 Notes 1. PD78F9436 only 2. If P50 to P53 have been set to input mode when a read instruction is executed to read from P50 to P53, a low-level input leakage current of up to -30 A flows during only one cycle. At all other times, the maximum leakage current is -3 A. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U15379EJ1V0DS 31 PD78F9436, 78F9456 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol Power supply currentNote 1 IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Conditions MIN. 5.0 MHz crystal oscillation VDD = 5.0 V 10% operation mode VDD = 3.0 V 10%Note 3 (C1 = C2 = 22 pF) VDD = 2.0 V 10%Note 3 Note 2 5.0 MHz crystal oscillation VDD = 5.0 V 10% HALT mode VDD = 3.0 V 10%Note 3 (C1 = C2 = 22 pF) VDD = 2.0 V 10%Note 3 Note 2 TYP. MAX. Unit 4.5 9 mA 1 2 mA 0.65 1.5 mA 1.4 2 mA 0.4 0.8 mA 0.19 0.42 mA 32.768 kHz crystal oscillation operation modeNote 4 (C3 = C4 = 22 pF, R1 = 220k) VDD = 5.0 V 10% 100 230 A VDD = 3.0 V 10% 70 160 A VDD = 2.0 V 10% 58 120 A 32.768 kHz crystal oscillation HALT modeNote 4 VDD = 5.0 V 10% 25 65 A VDD = 3.0 V 10% 7 29 A VDD = 2.0 V 10% 4 20 A VDD = 5.0 V 10% 28 70 A VDD = 3.0 V 10% 9.6 34 A VDD = 2.0 V 10% 6 25 A VDD = 5.0 V 10% 0.1 17 A VDD = 3.0 V 10% 0.05 5.5 A VDD = 2.0 V 10% 0.05 3.5 A 5.2 10.8 mA 1.4 3.8 mA 1.0 2.9 mA LCD not operating LCD operatingNote 5 Note 6 STOP mode 5.0 MHz crystal oscillation VDD = 5.0 V 10% A/D operating modeNote 7 VDD = 3.0 V 10%Note 3 (C1 = C2 = 22 pF) VDD = 2.0 V 10%Note 3 Note 2 Notes 1. The port current (including the current that flows to the on-chip pull-up resistor) is not included. 2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H) 3. Low-speed mode operation (when PCC is set to 02H) 4. When the main system clock is stopped 5. This is the current when the LCD controller/driver is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 0) is included in IDD2 (HALT mode). 6. When the LCD voltage amplifier is stopped (LCDON0 = 0, VAON0 = 0) 7. This is the total current that flows to VDD and AVDD. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 32 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Cycle time (minimum instruction execution time) Symbol TCY Conditions Operating with main system clock MIN. VDD = 2.7 to 5.5 V TYP. MAX. Unit 0.4 8.0 s 1.6 8.0 s 125 s Operating with subsystem clock 114 Capture input high-/low- tCPTH, level width tCPTL CPT90 10 TMI60 input frequency VDD = 2.7 to 5.5 V 0 4 MHz 0 275 kHz fTMI 122 s 0.1 s 1.8 s INTP0 to INTP3 10 s KR0 to KR3 10 s 10 s TMI60 input high-/lowlevel width tTIMH, tTIML VDD = 2.7 to 5.5 V Interrupt input high/low-level width tINTH, tINTL Key return input lowlevel width tKRL RESET low-level width tRSL TCY vs. VDD (main system clock) Cycle time TCY [ s] 60 10 8.0 Guaranteed operation range 1.0 0.4 0.1 1 2 3 4 5 6 Power supply voltage VDD (V) Data Sheet U15379EJ1V0DS 33 PD78F9436, 78F9456 (2) Serial interface 20 (SIO20) (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (internal clock output) Parameter SCK20 cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V SCK20 high-/low-level width tKH1, tKL1 VDD = 2.7 to 5.5 V SI20 setup time (to SCK20) tSIK1 VDD = 2.7 to 5.5 V SI20 hold time (from SCK20) tSI1 Delay time from tSO1 SCK20 to SO20 output VDD = 2.7 to 5.5 V R = 1 k, C = 100 pF Note VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY1/2-50 ns tKCY1/2-150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns MAX. Unit Note R and C are the load resistance and load capacitance of the SO20 output line. (b) 3-wire serial I/O mode (external clock input) Parameter SCK20 cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V SCK20 high-/low-level width tKH2, tKL2 VDD = 2.7 to 5.5 V SI20 setup time (to SCK20) tSIK2 VDD = 2.7 to 5.5 V SI20 hold time (from SCK20) tSI2 Delay time from tSO2 SCK20 to SO20 output SO20 setup time (with SS20, to SCK20) tKAS2 SO20 disable time (with SS20, from SCK20) tKDS2 VDD = 2.7 to 5.5 V R = 1 k, C = 100 pFNote VDD = 2.7 to 5.5 V MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns 120 ns 400 ns 240 ns 800 ns MAX. Unit 78125 bps 19531 bps VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V Note R and C are the load resistance and load capacitance of the SO20 output line. (c) UART mode (dedicated baud rate generator output) Parameter Transfer rate 34 Symbol Conditions VDD = 2.7 to 5.5 V Data Sheet U15379EJ1V0DS MIN. TYP. PD78F9436, 78F9456 (d) UART mode (external clock input) Parameter ASCK20 cycle time ASCK20 high-/lowlevel width Symbol tKCY3 tKH3, tKL3 Transfer rate ASCK20 rise/fall time Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tR, tF Data Sheet U15379EJ1V0DS MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 39063 bps 9766 bps 1 s 35 PD78F9436, 78F9456 AC Timing Test Points (excluding X1 and XT1 inputs) 0.8VDD 0.2VDD 0.8VDD Test points 0.2VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) 1/fXT tXTL tXTH VIH4 (MIN.) XT1 input VIL4 (MAX.) Capture Input Timing tCPTH tCPTL CPT90 TMI Timing 1/fTI tTIL tTIH TMI60 Interrupt Input Timing tINTL tINTH INTP0 to INTP3 Key Return Input Timing tKRL KR0 to KR3 36 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 RESET Input Timing tRSL RESET Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm SCK20 tSIKm SI20 tKSIm Input data tKSOm Output data SO20 Remark m = 1, 2 3-wire serial I/O mode (when using SS20): SS20 tKAS2 tKDS2 Output data SO20 UART mode (external clock input): tKCY3 tKL3 tKH3 tR tF ASCK20 Data Sheet U15379EJ1V0DS 37 PD78F9436, 78F9456 10-Bit A/D Converter Characteristics (TA = -40 to +85C, 1.8 V AVDD = VDD 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.5 V AVDD 5.5 V 0.2 0.4 %FSR 2.7 V AVDD < 4.5 V 0.4 0.6 %FSR 1.8 V AVDD < 2.7 V 0.8 1.2 %FSR Resolution Note Overall error Conversion time tCONV Note Zero-scale error AINL Full-scale errorNote Non-integral linearity Non-differential linearityNote Analog input voltage AINL Note INL DNL 4.5 V AVDD 5.5 V 14 100 s 2.7 V AVDD < 4.5 V 19 100 s 1.8 V AVDD < 2.7 V 28 100 s 4.5 V AVDD 5.5 V 0.4 %FSR 2.7 V AVDD < 4.5 V 0.6 %FSR 1.8 V AVDD < 2.7 V 1.2 %FSR 4.5 V AVDD 5.5 V 0.4 %FSR 2.7 V AVDD < 4.5 V 0.6 %FSR 1.8 V AVDD < 2.7 V 1.2 %FSR 4.5 V AVDD 5.5 V 2.5 LSB 2.7 V AVDD < 4.5 V 4.5 LSB 1.8 V AVDD < 2.7 V 8.5 LSB 4.5 V AVDD 5.5 V 1.5 LSB 2.7 V AVDD < 4.5 V 2.0 LSB 1.8 V AVDD < 2.7 V 3.5 LSB AVDD V VIAN 0 Note Excludes quantization error (0.05%) Remark 38 FSR: Full scale range Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 LCD Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol LCD output voltage variation range VLCD2 Doubler output VLCD1 Conditions MIN. TYP. MAX. Unit GAIN = 1 0.84 1.0 1.165 V GAIN = 0 1.26 1.5 1.74 V C1 to C4Note 1 = 0.47 F 2VLCD2 -0.1 2.0VLCD2 2.0VLCD2 V = 0.47 F 3VLCD2 -0.15 3.0VLCD2 3.0VLCD2 V Note 1 C1 to C4 Note 1 Tripler output VLCD0 C1 to C4 Voltage amplification wait timeNote 2 tVAWAIT GAIN = 0 GAIN = 1 = 0.47 F 0.5 s 5.0 VDD 5.5 V 2.0 s 4.5 VDD < 5.0 V 1.0 s 1.8 VDD < 4.5 V 0.5 s LCD output voltage differentialNote 3 (common) VODC IO = 5 A 0 0.2 V LCD output voltage differentialNote 3 (segment) VODS IO = 1 A 0 0.2 V Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VLC0 and VSS C3: A capacitor connected between VLC1 and VSS C4: A capacitor connected between VLC2 and VSS 2. This is the wait time from when voltage amplification is started (VAON0 = 1) until display is enabled (LCDON0 = 0). 3. The voltage differential is the difference between the segment and common signal output's actual and ideal output voltages. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Conditions MIN. Data retention power supply voltage VDDDR 1.8 Release signal set time tSREL 0 Data Sheet U15379EJ1V0DS TYP. MAX. Unit 5.5 V s 39 PD78F9436, 78F9456 Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Oscillation Stabilization Wait Time (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Oscillation stabilization wait timeNote 1 Symbol Conditions tWAIT MIN. TYP. MAX. 15 Unit Release by RESET 2 /fX s Release by interrupt Note 2 s Notes 1. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. 12 15 17 2. Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time selection register (OSTS). Remark 40 fX: Main system clock oscillation frequency Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 Flash Memory Write/Erase Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V) Parameter Operating frequency Symbol fX Conditions VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 1.0 5 MHz 1.0 1.25 MHz 7 mA Write currentNote (VDD pin) IDDW When VPP supply voltage = VPP1 Write currentNote (VPP pin) IPPW When VPP supply voltage = VPP1 12 mA Erase currentNote (VDD pin) IDDE When VPP supply voltage = VPP1 7 mA Erase currentNote (VPP pin) IPPE When VPP supply voltage = VPP1 100 mA Unit erase time ter 1 s Total erase time tera 20 s 20 Times 0.2VDD V 10.3 V Write count VPP supply voltage During fX = 5.0 MHz operation During fX = 5.0 MHz operation 0.5 1 Erase/write are regarded as 1 cycle VPP0 In normal operation VPP1 During flash memory programming 0 9.7 10.0 Note The port current (including the current that flows to the on-chip pull-up resistors) is not included. Data Sheet U15379EJ1V0DS 41 PD78F9436, 78F9456 8. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFRENCE VALUES) (1) Characteristics curves of voltage amplification stabilization time The following shows the characteristics curves of the time from the start of voltage amplification (VAON0 = 1) and the changes in the LCD output voltage (when GAIN is set as 1 (using the 3 V display panel)). LCD output voltage/Voltage amplification time 5.5 5 VDD = 4.5 V VDD = 5 V VDD = 5.5 V 4.5 LCD output voltage [V] 4 3.5 VLCD0 3 2.5 VLCD1 2 1.5 VLCD2 1 0.5 0 0 500 1000 1500 2000 2500 Voltage amplification time [ms] 42 Data Sheet U15379EJ1V0DS 3000 3500 4000 PD78F9436, 78F9456 (2) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage. LCD output voltage/ Temperature (When GAIN = 1) VLCD2 5 VLCD1 VLCD0 LCD output voltage [V] 4 3 2 1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C] LCD output voltage/ Temperature (When GAIN = 0) 5 VLCD2 VLCD1 VLCD0 LCD output voltage [V] 4 3 2 1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C] Data Sheet U15379EJ1V0DS 43 PD78F9436, 78F9456 9. PACKAGE DRAWINGS 64-PIN PLASTIC TQFP (12x12) A B 48 detail of lead end 33 32 49 S P T C D R L U 64 Q 17 16 1 F G J H I M ITEM K S M N S NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A B 14.00.2 12.00.2 C 12.00.2 D F 14.00.2 1.125 G 1.125 H 0.32 +0.06 -0.10 I 0.13 J 0.65 (T.P.) K 1.00.2 L 0.5 M 0.17 +0.03 -0.07 N 0.10 P 1.0 Q 0.10.05 R +4 3 -3 S 1.10.1 T 0.25 U 0.60.15 P64GK-65-9ET-3 44 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 10. RECOMMENDED SOLDERING CONDITIONS The PD78F9436 and 78F9456 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions PD78F9436-9ET: 64-pin plastic TQFP (12 x 12) PD78F9456-9ET: 64-pin plastic TQFP (12 x 12) Soldering Method Soldering Conditions Recommended Condition Symbol Interface reflow Package peak temperature: 235C, Time:30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) IR35-107-2 VPS Package peak temperature: 215C, Time:40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) VP15-107-2 Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Note After opening the dry peak, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U15379EJ1V0DS 45 PD78F9436, 78F9456 APPENDIX A. DIFFERENCES BETWEEN PD78F9436, 78F9456 AND MASK ROM VERSIONS The PD78F9436 and 78F9456 have flash memory in place of the internal ROM of the mask ROM versions. Differences between the PD78F9436 and 78F9456 and the mask ROM versions are shown in Table A-1. Table A-1. Differences Between PD78F9436, 78F9456 and Mask ROM Versions Part Number PD78F9436 Item Internal memory Flash Memory Versions ROM 16 KB High-speed RAM 512 bytes LCD display RAM 5 x 4 bits PD78F9456 Mask ROM Versions PD789435 12 KB 15 x 4 bits 16 KB 5 x 4 bits IC pin Not available Available VPP pin Available Not available Pull-up resistors 30 (software control: 30) Electrical specifications Refer to the relevant data sheet. 20 (software control: 20) PD789436 34 (software control: 30, mask option: 4) PD789455 PD789456 12 KB 16 KB 15 x 4 bits 24 (software control: 20, mask option: 4) Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. 46 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the PD78F9436 and 78F9456. Language Processing Software RA78K0SNotes 1, 2, 3 Assembler package common to 78K/0S Series Notes 1, 2, 3 C compiler package common to 78K/0S Series CC78K0S Notes 1, 2, 3, DF789456 Notes 1, 2, 3 CC78K0S-L Device file for PD789426, 789436, 789446, 789456 Subseries C compiler library source file common to 78K/0S Series Flash Memory Writing Tools Flashpro III (Part No. FL-PR3Note 4, PG-FP3) Flash programmer dedicated to on-chip flash memory microcontroller FA-64GK-9ETNote 4 Flash memory writing adapter for 64-pin plastic TQFP (GK-9ET type) Debugging Tools IE-78K0S-NS In-circuit emulator This is an in-circuit emulator for debugging the hardware and software of an application system using the 78K/0S Series. It supports the integrated debugger (ID78K0S-NS). It is used with an AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A In-circuit emulator This is a board to expand the functions of the IE-78K0S-NS. The addition of this board enhances debugging functions such as the coverage, tracer, and timer functions. IE-70000-MC-PS-B AC adapter This is the adapter for supplying power from an AC-100 to 240 V outlet. IE-70000-98-IF-C Interface adapter This adapter is needed when a PC-9800 series PC (except notebook type) is used as the host machine for an IE-78K0S-NS (supports C bus). IE-70000-CD-IF-A PC card interface This PC card and interface cable are needed when a PC-9800 series notebook-type PC is used as the host machine for an IE-78K0S-NS (supports PCMCIA socket). IE-70000-PC-IF-C Interface adapter This adapter is needed when an IBM PC/ATTM or compatible PC is used as the host machine for an IE-78K0S-NS (supports ISA bus). IE-70000-PCI-IF-A Interface adapter This adapter is needed when a PC that includes a PCI bus is used as the host machine for an IE-78K0S-NS. IE-789436-NS-EM1 Emulation board This is an emulation board for emulating the peripheral hardware inherent to PD789426, 789436 Subseries devices. It is used with an in-circuit emulator. IE-789456-NS-EM1 Emulation board This is an emulation board for emulating the peripheral hardware inherent to PD789446, 789456 Subseries devices. It is used with an in-circuit emulator. NP-64GKNote 4 Emulator probe This is a cable that is used to connect an in-circuit emulator to the target system. It is for a 64-pin plastic TQFP (GK-9ET type). SM78K0SNotes 1, 2 System simulator common to 78K/0S Series ID78K0S-NS Notes 1, 2 Notes 1, 2 DF789456 Integrated debugger common to 78K/0S Series Device file for PD789426, 789436, 789446, 789456 Subseries Real-Time OS MX78K0SNotes 1, 2 OS for 78K/0S Series Data Sheet U15379EJ1V0DS 47 PD78F9436, 78F9456 Notes 1. Based on PC-9800 Series (Japanese WindowsTM) 2. Based on IBM PC/AT compatibles (Japanese/English Windows) 3. Based on HP9000 Series 700TM (HP-UXTM), or SPARCstationTM (SunOSTM, SolarisTM) 4. This product is manufactured by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). Remark 48 The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789456. Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to devices Document Name Document No. PD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 Data Sheet U14493E PD78F9436, 78F9456 Data Sheet This document PD789426, 789436, 789446, 789456 Subseries User's Manual U15075E 78K/0S Series User's Manual Instructions U11047E 78K/0, 78K/0S Series Application Note Flash Memory Write U14458E Documents related to development tools (user's manuals) Document Name RA78K0S Assembler Package Document No. Operation U11622E Language U11599E Structured Assembly Language U11623E Operation U11816E Language U11817E SM78K0S, SM78K0, System Simulator Ver.2.10 or later Windows Based Operation U14611E SM78K Series System Simulator Ver 2.10 or Later External Part User Open Interface Specifications U15006E ID78K0-NS, ID78K0S-NS Integrated Debugger Ver.2.20 or later Windows Based Operation U14910E CC78K0S C Compiler IE-78K0S-NS In-circuit Emulator U13549E IE-789436-NS-EM1 Emulation Board To be prepared IE-789456-NS-EM1 Emulation Board To be prepared PG-FP3 Flash Memory Programmer U13502E Documents related to embedded software (user's manuals) Document Name 78K/0S Series OS MX78K0S Fundamental Document No. U12938E Other documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products & Packages - (CD-ROM) X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U15379EJ1V0DS 49 PD78F9436, 78F9456 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM and FIP are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. 50 Data Sheet U15379EJ1V0DS PD78F9436, 78F9456 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U15379EJ1V0DS 51 PD78F9436, 78F9456 * The information in this document is current as of April, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4